Numerous electronic technologies such as digital computers, video equipment, and telephone systems have facilitated increased productivity and reduced costs in processing information in most areas of business, science, and entertainment. The electronic systems often include integrated circuits that process signals. Accurate signal processing is important for proper performance. However, there are a number of factors that can impact accurate signal processing. Resistance and capacitance balance or lack thereof can have a significant impact on signal processing performance.
High speed parallel buses in silicon interposers usually have strong resistance and capacitance (RC) effects due to fine metal size and spacing. For example, conventional high bandwidth memory (HBM) over interposer's metal width is approximately 1 um. Next generation HBM could run at speeds of approximately 4 Gbps, and the theoretical valid timing window is only 125 ps. It can be critical to keep resistance and capacitance (RC) time constants equal for multiple signals, otherwise introduced skew could easily violate or “kill” a timing margin. FIG. 1 is a block diagram of a conventional re-distribution layer (RDL) mesh grid. The system of FIG. 1 includes metal one M1 layer components (shown in light gray), metal two M2 layer components (shown in dark gray), and redistribution layer (RDL) components (shown in lozenges with a cris-cross pattern). It is appreciated the M1, layer, M2 layer, and RDL layer can be separate layers in the silicon device and as projected into the illustration of FIG. 1. In one embodiment, both the M2 and RDL layers can have ground characteristics. The signal capacitance of metal layer 1 is quite different from the signal capacitance of metal layer 2, due to the extra capacitance between metal layer 1 to RDL.